The present invention relates to a semiconductor device and a method for fabricating the same; and more particularly, to a bulb-shaped recess gate and a method for fabricating the same.
Typically, a recess gate of a semiconductor device is considered as a special structure which cannot be excluded from the fabrication of the semiconductor device. The recess gate increases electric properties including a threshold voltage, and a refresh time which may be generated due to a decreased channel area of a gate as a device pattern becomes densified. The recess gate also increases a length of the gate undergoing a gate patterning process, resulting in an increased channel area, thereby improving a device property.
However, as a device size has been reduced, patterns become smaller and a distance between the devices becomes reduced. Accordingly, it is required to increase the channel area.
Recently, a bulb-shaped recess gate increasing the channel area by increasing an area of a bottom portion of the recess gate has been suggested.
FIG. 1 illustrates a typical method for fabricating a bulb-shaped recess gate.
A bulb-shaped recess pattern 12 includes a neck pattern 12A and a ball pattern 12B, both formed over a substrate 11.
A gate oxide layer 13 is formed over surfaces of bulb-shaped recess pattern 12 and substrate 11. Then, a polysilicon layer 14 filling bulb-shaped recess pattern 12, and used as a gate electrode, is formed over gate oxide layer 13.
As for bulb-shaped recess pattern 12, during forming polysilicon layer 14 which is the gate electrode, the inside of neck pattern 12A is filled with polysilicon layer 14 before ball pattern 12B is filled with the polysilicon layer 14. As a result, a void V1 may be generated.
FIGS. 2A and 2B are micrographs illustrating a void V2 typically generated during forming a polysilicon layer.
Void V2 generated during the formation of the polysilicon layer does not typically affect a device property. However, if a width of a neck pattern of a bulb-shaped recess gate is small while that of a ball pattern of the bulb-shaped recess gate is large, a size of void V2 may be increased. The increased size of void V2 may then reduce a thickness of the polysilicon layer. Thus, an electric property of the device may be decreased.
A method for increasing the width of the neck pattern may be suggested to reduce the size of void V2. However, increasing the width of the neck pattern reduces an overlay margin between the neck pattern and a gate electrode formed over the neck pattern, thereby producing a mis-alignment, resulting in difficulties in device fabrication.